1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor memory including a memory cell array and a peripheral circuit thereof.
2. Description of the Background Art
FIGS. 26 and 29 to 33 are sectional views showing a background method of manufacturing a semiconductor memory in sequential order. The semiconductor memory includes a region in which a memory cell array is formed (hereinafter referred to as xe2x80x9cmemory cell array forming regionxe2x80x9d) and a region in which a peripheral circuit of the memory cell array is formed (hereinafter referred to as xe2x80x9cperipheral circuit forming regionxe2x80x9d). A memory cell array constituting a DRAM, for example, is formed in the memory cell array forming region, and a peripheral circuit including a sense amplifier, a sub-decoder and the like is formed in the peripheral circuit forming region. Referring to FIGS. 26 and 29 to 33, the background method of manufacturing the semiconductor memory will be described.
As shown in FIG. 26, a plurality of bit lines 103 are formed in the memory cell array forming region, and a bit line 106 is formed in the peripheral circuit forming region adjacent to the memory cell array forming region. Then, an insulation layer 118 is formed in the memory cell array forming region and peripheral circuit forming region to cover the bit lines 103 and 106. The insulation layer 118 is made of a silicon oxide film, for example.
Next, a plurality of storage node contact plugs (hereinafter referred to as xe2x80x9cSC plugsxe2x80x9d) 107 are provided in the insulation layer 118 in the memory cell array forming region. The SC plugs 107 have top surfaces exposed from the insulation layer 118 and are arranged in a matrix in the direction perpendicular to the film thickness direction of the insulation layer 118. The SC plugs 107 are made of doped polysilicon or metal, for example.
The bit lines 103 each have a stacked structure of a conductive film 101 made of doped polysilicon, metal or the like and a silicon nitride film 102. The bit line 106 also has a stacked structure of a conductive film 104 made of doped polysilicon, metal or the like and a silicon nitride film 105, similarly to the bit lines 103.
Although not shown, a semiconductor substrate provided with a plurality of semiconductor elements is present under the insulation layer 118. A plurality of MOS transistors are formed in a matrix on the semiconductor substrate in the memory cell array forming region while a transistor which constitutes the peripheral circuit is formed in the semiconductor substrate in the peripheral circuit forming region. The SC contact plugs 107 are each provided for each of the MOS transistors formed on the semiconductor substrate and electrically connected to one of source/drain regions of each MOS transistor. The bit lines 103 and 106 are electrically connected to the other source/drain region of each MOS transistor to which no SC plug 107 is connected.
Next, a silicon nitride film 108 and an insulation layer 109 made of, e.g., a silicon oxide film are stacked in this order on the upper surfaces of the insulation layer 118 and the SC plugs 107. Accordingly, the silicon nitride film 108 and insulation layer 109 are provided in the memory cell array forming region and peripheral circuit forming region. Then, a photoresist (not shown) is formed over the insulation layer 109 and the photoresist is exposed using a photomask (not shown) having a predetermined mask pattern. As a result, the mask pattern of the photomask is transferred to the photoresist. The photoresist is then developed, and a predetermined opening pattern is formed on the photoresist.
Next, the insulation layer 109 and silicon nitride film 108 are etched using the photoresist having the predetermined opening pattern formed thereon as a mask. Accordingly, a plurality of openings 110 for exposing the SC plugs 107 are formed in the insulation layer 109 and silicon nitride film 108 in the memory cell array forming region, and a trench 120 is further formed in the insulation layer 109 and silicon nitride film 108 at the border between the memory cell array forming region and peripheral circuit forming region. The photomask used for forming the openings 110 and the trench 120 will be described later in detail.
Next, a polysilicon film is entirely formed, part of which is present above the openings 110 and the trench 120 is removed by a CMP method. Accordingly, a lower electrode 111 of a capacitor made of a polysilicon film is formed on the surface of each of the openings 110, and a guard ring film 121 made of a polysilicon film is formed on the surface of the trench 120.
FIG. 27 is a plan view showing the structure of FIG. 26 viewed from an arrow C. FIG. 27 illustrates the SC plugs 107, bit lines 103 and 106 in broken lines which actually do not appear in the plan view. FIG. 26 is a sectional view taken along the line Dxe2x80x94D of FIG. 27.
As shown in FIG. 27, the openings 110 are each provided for each of the SC plugs 107 and arranged in a matrix in the direction perpendicular to the film thickness direction of the insulation layer 109. Specifically, the openings 110 are arranged at a pitch P200 in the column direction and at a pitch P100 in the row direction.
The trench 120 is formed to surround the openings 110. Part of the trench 120 extending in the column direction is spaced at a pitch P101 from the most adjacent ones of the openings 110 aligned in the column direction, while part of the trench 120 extending in the row direction is spaced at a pitch P201 from the most adjacent ones of the openings 110 aligned in the row direction. The xe2x80x9ccolumn directionxe2x80x9d and xe2x80x9crow directionxe2x80x9d denote the left-to-right direction and top-to-bottom direction of the drawing sheet, respectively.
FIG. 28 is a plan view showing a photomask 300 used for forming the openings 110 and the trench 120 shown in FIG. 27. The photomask 300 is a positive-type photoresist, for example.
As shown in FIG. 28, the photomask 300 is provided with a mask pattern 301 including a plurality of patterns 200 corresponding to the openings 110 and a pattern 201 corresponding to the trench 120. The patterns 200 are arranged in a matrix at a pitch P210 in the column direction and at a pitch P110 in the row direction.
The pattern 201 is formed to surround the patterns 200. Part of the pattern 201 extending in the column direction is spaced at a pitch P111 from the most adjacent ones of the patterns 200 aligned in the column direction, while part of the pattern 201 extending in the row direction is spaced at a pitch P211 from the most adjacent ones of the patterns 200 aligned in the row direction.
In the case where the mask pattern 301 is transferred to the photoresist on an equal scale, the pitches P110, P111, P210 and P211 correspond to the pitches P100, P101, P200 and P201 shown in FIG. 27, respectively. In the case where the mask pattern 301 is transferred to the photoresist on a reduced scale, e.g., on a one-fifth scale, the pitches P110, P111, P210 and P211 are five times the pitches P100, P101, P200 and P201 shown in FIG. 27, respectively.
Next, as shown in FIG. 29, a resist 130 is formed on the insulation layer 109 and guard ring film 121 in the peripheral circuit forming region. Accordingly, the trench 120 is filled with the resist 130. Then, as shown in FIG. 30, the insulation layer 109 is selectively etched using the resist 130 as a mask to remove the insulation layer 109 in the memory cell array forming region. As shown in FIG. 31, the resist 130 is then removed.
Next, as shown in FIG. 32, a dielectric film 112 of a capacitor is formed on the lower electrode 111, guard ring film 121 and silicon nitride film 108 in the memory cell array forming region, and an upper electrode 113 of the capacitor is formed on the dielectric film 112. Accordingly, a plurality of capacitors 115 are formed in the memory cell array forming region. An insulation layer 140 made of, e.g., a silicon oxide film is formed over the insulation layer 109 and upper electrode 113.
Next, as shown in FIG. 33, a contact plug 157 is formed in the insulation layers 109, 118 and 140 and silicon nitride films 105 and 108 in the peripheral circuit forming region to be in contact with the conductive film 104 of the bit line 106. The contact plug 157 is made of, e.g., tungsten having its upper surface exposed from the insulation layer 140.
A metal wire 150 is formed on the insulation layer 140 to be in contact with the contact plug 157. A metal wire 151 electrically insulated from the metal wire 150 is further formed on the insulation layer 140. The metal wires 150 and 151 are made of, e.g., aluminum.
With the above-described steps, the memory cell array constituting the DRAM is formed in the memory cell array forming region and the peripheral circuit of the memory cell array is formed in the peripheral circuit forming region.
With the aforementioned background method of manufacturing the semiconductor memory, isotropic etching is usually performed using fluoric acid or the like when performing the step shown in FIG. 30, that is, when masking the peripheral circuit forming region and selectively removing the insulation layer 109 in the memory cell array forming region. Thus, fluoric acid may be impregnated into the insulation layer 109 in the masked peripheral circuit forming region in the case where the guard ring film 121 is not provided unlike the aforementioned background method of manufacturing the semiconductor memory, which may cause the insulation layer 109 in the peripheral circuit forming region to be also removed. This may create a step height on the upper surface of the upper insulation layer 140, causing defocus and the like in a photolithography process for forming the metal wires 150 and 151 on the insulation layer 140. As a result, it has been difficult to form the metal wires 150 and 151 in a desired shape.
With the above-described method, however, the guard ring film 121 is formed at the border between the memory cell array forming region and peripheral circuit forming region, preventing fluoric acid or the like from being impregnated into the insulation layer 109 in the peripheral circuit forming region as shown in FIG. 26, which prevents the insulation layer 109 in the peripheral circuit forming region from being removed. As a result, a step height is prevented from appearing on the upper surface of the upper insulation layer 140, making easier to form the metal wires 150 and 151 in a desired shape.
A technique of preventing a step height on the upper insulation layer by providing the above-described guard ring film 121 at the border between the memory cell array forming region and peripheral circuit forming region is disclosed in Japanese Patent Application Laid-Open No. 7-7084.
With the above-described method, however, the outermost ones of the openings 110 arranged in a matrix may be formed in a size greatly different from a desired size unlike the rest of the openings 110 in the case where the pitch of the patterns 200 and that between the pattern 201 and the most adjacent ones of the patterns 200 are not in agreement with each other in the mask pattern 301. This will be described below in detail.
As shown in FIG. 28, the patterns 200 corresponding to the openings 110 are arranged at the pitch P210 in the column direction and at the pitch P110 in the row direction. When transferring such patterns arranged at predetermined pitches to a photoresist, exposing conditions are usually adjusted in accordance with pitches of patterns to be transferred, i.e., the pitches P110 and P210 in this case. In other words, when transferring patterns arranged with periodicity to a photoresist, exposing conditions are adjusted in accordance with the periodicity of the patterns to be transferred. Therefore, the patterns can be transferred to a photoresist with reliability even if they are minute patterns.
However, in the case where the pitch P111 between part of the pattern 201 extending in the column direction and the most adjacent ones of the patterns 200 aligned in the column direction is not in agreement with the pitch P110 of the patterns 200 in the row direction, the periodicity in the row direction is broken. This may cause the most adjacent ones of the patterns 200 in the column direction spaced from the pattern 201 at the pitch P111 to be transferred to a photoresist in a size greatly different from a desired size.
Further, in the case where the pitch P211 between part of the pattern 201 extending in the row direction and the most adjacent ones of the patterns 200 aligned in the row direction is not in agreement with the pitch P210 of the patterns 200 in the column direction, the periodicity in the column direction is broken. This may cause the most adjacent ones of the patterns 200 in the row direction spaced from the pattern 201 at the pitch P211 to be transferred to a photoresist in a size greatly different from a desired size.
As described, depending on the relationship between the pattern 201 and patterns 200, the outermost ones of the patterns 200 arranged in a matrix may be transferred to a photoresist in a size greatly different from a desired size unlike the rest of the patterns 200. Thus, when forming the openings 110 using the developed photoresist as a mask, the outermost ones of the openings 110 arranged in a matrix may be formed in a size greatly different from a desired size.
For instance, when the pitch P111 shown in FIG. 28 is smaller than the pitch P110, the outermost ones of the patterns 200 aligned in the column direction are transferred to the photoresist in a size greater than a desired size. Thus, the outermost ones of the openings 110 aligned in the column direction are formed in a size greater than a desired size. When the pitch P211 shown in FIG. 28 is smaller than the pitch P210, the outermost ones of the patterns 200 aligned in the row direction are transferred to the photoresist in a size greater than a desired size. Thus, the outermost ones of the openings 110 aligned in the row direction are formed in a size greater than a desired size. In this manner, when the openings 110 are formed in a size greater than a desired size, adjacent ones of the openings 110 may communicate with each other, and lower electrodes 111 may be short-circuited between adjacent ones of the capacitors 150. This may reduce the reliability of a semiconductor memory.
Further, when the pitch P111 shown in FIG. 28 is greater than the pitch P110, for instance, the outermost ones of the patterns 200 aligned in the column direction are transferred to the photoresist in a size smaller than a desired size. Thus, the outermost ones of the openings 110 aligned in the column direction are formed in a size smaller than a desired size. When the pitch P211 shown in FIG. 28 is greater than the pitch P210, the outermost ones of the patterns 200 aligned in the row direction are transferred to the photoresist in a size smaller than a desired size. Thus, the outermost ones of the openings 110 aligned in the row direction are formed in a size smaller than a desired size. In this manner, when the openings 110 are formed in a size smaller than a desired size, the surface area of the lower electrode 111 formed on each of the openings 110 may not be ensured sufficiently, resulting in a reduction in capacity of the capacitors 115.
Furthermore, when the openings 110 are formed in a size smaller than a desired size, the contact area of the lower electrode 111 and the SC plugs 107 and silicon nitride film 108 is reduced, causing the lower electrode 111 to easily fall down after the insulation layer 109 in the memory cell array forming region is removed. This may cause so-called xe2x80x9cpattern discontinuityxe2x80x9d in which the lower electrode 111 falls down after the step shown in FIG. 26 is performed.
As described above, a semiconductor memory may be degraded in reliability even when the openings 110 are formed in a size smaller than a desired size.
Further, as shown in FIG. 27, the trench 120 is formed linearly in the column and row directions, so that the guard ring film 121 formed on the surface of the trench 120 also extends linearly. Thus, the guard ring film 121 easily falls down in the direction perpendicular to the extending direction thereof after the step shown in FIG. 30 is performed. Specifically, as shown in FIG. 30, a sidewall of the guard ring film 121 in the peripheral circuit forming region is supported by the insulation layer 109, whereas there is nothing provided to support the other sidewall of the guard ring film 121 in the memory cell array forming region, causing the guard ring film 121 to easily fall down to the side of the memory cell array forming region. This may cause a drawback in the reliability of the semiconductor memory.
An object of the present invention is to provide a technique of improving a semiconductor memory in reliability.
A first aspect of the present invention is directed to a method of manufacturing a semiconductor memory including a memory cell array forming region and a peripheral circuit forming region adjacent to the memory cell array forming region. The method includes the following steps (a) through (e). The step (a) is to form an insulation layer in the memory cell array forming region and the peripheral circuit forming region. The step (b) is to form a plurality of openings in the insulation layer in the memory cell array forming region and forming a trench in the insulation layer at the border between the memory cell array forming region and the peripheral circuit forming region. The step (c) is to form a lower electrode of a capacitor on a surface of each of the plurality of openings. The step (d), after the step (c), is to fill the trench with a resist and form the resist on the insulation layer in the peripheral circuit forming region. The step (e) is to selectively etch the insulation layer using the resist as a mask. The step (b) includes the following steps (b-1) through (b-5). The step (b-1) is to prepare a photomask provided with a mask pattern including a plurality of first patterns corresponding to the plurality of openings, arranged at a predetermined pitch, a first dummy pattern aligned linearly with the plurality of first patterns at the predetermined pitch from the most adjacent one of the plurality of first patterns, and a second pattern corresponding to the trench. The step (b-2) is to form a photoresist on the insulation layer. The step (b-3) is to expose the photoresist using the photomask to transfer the mask pattern to the photoresist. The step (b-4) is to developing the photoresist, after the step (b-3). The step (b-5) is to etch the insulation layer using the photoresist as a mask to form the plurality of openings and the trench, after the step (b-4). The first dummy pattern is not transferred to the photoresist in the step (b-3).
Since the first dummy pattern is provided and spaced from the plurality of first patterns corresponding to the plurality of openings at the same pitch as that of the plurality of first patterns, the periodicity is maintained in the arrangement direction of the plurality of first patterns. This allows the outermost ones of the plurality of first patterns spaced at a predetermined pitch from the first dummy pattern to be transferred to the photoresist without significantly deviating from a desired size. Therefore, the outermost one of the plurality of openings can be formed close to a desired shape. As a result, the occurrence of pattern discontinuity and the like can be suppressed, which improves the semiconductor memory in reliability.
Further, the trench is formed at the border between the memory cell array forming region and peripheral circuit forming region, and the resist fills the trench. Thus, the insulation layer in the peripheral circuit forming region as masked is not etched when the step (e) is performed.
A second aspect of the present invention is directed to a method of manufacturing a semiconductor memory including a memory cell array forming region and a peripheral circuit forming region adjacent to the memory cell array forming region. The method includes the following steps (a) through (e). The step (a) is to form an insulation layer in the memory cell array forming region and the peripheral circuit forming region. The step (b) is to form a plurality of openings in the insulation layer in the memory cell array forming region and forming a trench in the insulation layer at the border between the memory cell array forming region and the peripheral circuit forming region. The step (c) is to form a lower electrode of a capacitor on a surface of each of the plurality of openings and forming a guard ring film on a surface of the trench. The step (d), after the step (c), is to form a resist on the insulation layer in the peripheral circuit forming region. The step (e) is to selectively etch the insulation layer using the resist as a mask. The step (b) includes the following steps (b-1) through (b-5). The step (b-1) is to prepare a photomask provided with a mask pattern including a plurality of first patterns corresponding to the plurality of openings, arranged at a predetermined pitch, a first dummy pattern aligned linearly with the plurality of first patterns at the predetermined pitch from the most adjacent one of the plurality of first patterns and a second pattern corresponding to the trench. The step (b-2) is to form a photoresist on the insulation layer. The step (b-3) is to expose the photoresist using the photomask to transfer the mask pattern to the photoresist. The step (b-4) is to develop the photoresist, after the step (b-3). The step (b-5) is to etch the insulation layer using the photoresist as a mask to form the plurality of openings and the trench, after the step (b-4). The first dummy pattern is not transferred to the photoresist in the step (b-3).
Since the first dummy pattern is provided and spaced from the plurality of first patterns at the same pitch as that of the plurality of first patterns, the periodicity is maintained in the arrangement direction of the plurality of first patterns. Therefore, the outermost one of the plurality of openings can be formed close to a desired shape. As a result, the occurrence of pattern discontinuity and the like can be suppressed, which improves the semiconductor memory in reliability.
Further, the guard ring film is formed at the border between the memory cell array forming region and peripheral circuit forming region. Thus, the insulation layer in the peripheral circuit forming region as masked is not etched when the step (e) is performed.
A third aspect of the present invention is directed to a method of manufacturing a semiconductor memory including a memory cell array forming region and a peripheral circuit forming region adjacent to the memory cell array forming region. The method includes the following steps (a) through (e). The step (a) is to form an insulation layer in the memory cell array forming region and the peripheral circuit forming region. The step (b) is to form an opening in the insulation layer in the memory cell array forming region and forming a meandering trench in the insulation layer at the border between the memory cell array forming region and the peripheral circuit forming region. The step (c) is to form a lower electrode of a capacitor on a surface of the opening and forming a guard ring film on a surface of the trench. The step (d), after the step (c), is to form a resist on the insulation layer in the peripheral circuit forming region. The step (e) is to selectively etch the insulation layer using the resist as a mask.
Since the guard ring film is formed at the border between the memory cell array forming region and peripheral circuit forming region, the insulation layer in the peripheral circuit forming region as masked is not etched when the step (e) is performed.
Further, the trench meanders, and therefore, the guard ring film formed in the trench also meanders. Thus, the guard ring film is unlikely to fall down after the step (e) is performed as compared to the case of forming the guard ring film in a trench that extends linearly. As a result, the semiconductor memory is improved in reliability.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.